The present invention relates to semiconductor design technology, and more particularly, to a control circuit for controlling a bit line sense amplifier array.
As a cell size and a wire width are decreased, a voltage level of a power supply voltage is decreased. Therefore, it is required to develop a design technology suitable for low-power condition. Further, it is required to reduce the power consumption of a semiconductor memory device.
FIG. 1 is a block diagram showing a bit line sense amplifier array and a peripheral circuit included in a conventional semiconductor memory device.
As shown, the conventional semiconductor memory device includes a sense amplifier driving control unit 10 for generating driving control signals SAN, BLEQ and SAP in response to an active signal ACT; a column address decoder 20 for generating a column selection signal YI<0:255> by decoding a column address signal YA<0:7>; and a bit line sense amplifier array 30 for receiving the column selection signal YI<0:255> and the driving control signals SAN, BLEQ and SAP.
The bit line sense amplifier array 30 generates a driving voltage according to the driving control signals SAN, BLEQ and SAP, and a bit line sense amplifier supplied with the driving voltage amplifies a data input to a bit line pair BL and /BL.
Herein, the column selection signal YI<0:255> is for reading the amplified data of the bit line pair BL and /BL for a data access operation, e.g., a read operation. That is, the column selection signal YI<0:255> is used for reading a required data among amplified data of 256 bit line pairs.
FIG. 2 is a block diagram depicting the bit line sense amplifier array 30 shown in FIG. 1.
As shown, the bit line sense amplifier array 30 includes a plurality of driving voltage generation units 31A and 32A for receiving the driving control signals SAN, BLEQ and SAP in order to generate a driving voltage; and a plurality of bit line sense amplifier mats 31B and 32B each of which includes a plurality of bit line sense amplifiers, e.g., SA1 to SA4, for performing an amplifying operation using the driving voltage. Herein, a structure of the driving voltage generation unit 31A is same to that of the driving voltage generation unit 32A, and a structure of the bit line sense amplifier mat 31B is same to that of the bit line sense amplifier mat 32B.
A pull-up control signal SAP among the driving control signals is input to a gate of a first n-type metal oxide semiconductor (NMOS) transistor NM1 so that an external power supply voltage VDD is supplied to a pull-up node RTO1. A pull-down control signal SAN is input to a gate of a second NMOS transistor NM2 so that a voltage level of a pull-down node SB1 is decreased to a ground voltage VSS. An equalization signal BLEQ is input to an equalization unit 40A connected between the pull-up node RTO1 and the pull-down node SB1 in order to equalize voltage levels loaded on the pull-up node RTO1 and the pull-down node SB1.
Further, the equalization signal BLEQ is also input to a bit line equalization unit (not shown) connected between a bit line pair BL and /BL coupled to the bit line sense amplifier in order to equalize a voltage level of the bit line BL and a voltage level of the bit line bar /BL.
FIG. 3 is a timing diagram showing an operation of the conventional semiconductor memory device.
When the active signal ACT is a logic high level, the equalization signal BLEQ is inactivated and the bit line pair BL and /BL has a small voltage difference. Thereafter, the pull-up control signal SAP and the pull-down control signal SAN are activated as a logic high level and, thus, a voltage level of the pull-up node RTO1 becomes the external power supply voltage VDD and a voltage level of the pull-down node SB1 becomes the ground voltage VSS.
Each bit line sense amplifier receives the voltages loaded on the pull-up node RTO1 and the pull-down node SB1 in order to amplify each data input to each bit line pair BL and /BL. Thereafter, the amplified data are read out by the column selection signal YI<0:255>.
Meanwhile, the pull-up control signal SAP and the pull-down signal SAN are generated as shown in the timing diagram. Herein, referring to FIG. 2, the pull-up control signal SAP and the pull-down control signal SAN are input to the all of the bit line sense amplifiers included in the bit line sense amplifier array 30 at the same time. That is, all of the bit line sense amplifiers included in the bit line sense amplifier array 30 perform a pull-up and a pull-down operations according to the pull-up and the pull-down control signals SAP and SAN.
Therefore, an IR drop due to the power consumption for the operations of the bit line sense amplifiers occurs at resistors, e.g., R1 and R2, shown in FIG. 2. Due to this problem, a higher voltage than a needed minimum external voltage VDD is needed. Further, due to unstable operation, a delay time tRCD between a row address strobe (RAS) signal to a column address strobe (CAS) signal is increased.